I’m Matthew!

Electrical Engineering @ UWaterloo

latest essay – the vagrant west

Matthew Chen

01About

Recently 🪴

  • studying Electrical Engineering @UWaterloo
  • interning at Altera, network on chip (NOC) IP team
  • experimenting on FPGAs as a researcher and hobbyist
  • helping architect an ASIC ray tracing engine

Things I like 💡

I enjoy having meaningful conversations with people from different backgrounds, please reach out.

Fall in love with some activity, and do it! Nobody ever figures out what life is all about, and it doesn’t matter. Explore the world. Nearly everything is really interesting if you go into it deeply enough. Work as hard and as much as you want to on the things you like to do the best.

Richard Feynman

02Projects

2nd Order Delta-Sigma ADC

2026

A continuous-time 2nd-order ΔΣ ADC, built with a 3-bit flash sampler at 10 MHz/sample and DWA element rotation, FPGA backend filtering + decimation, modelled in Python for loop stability, noise shaping, and ELD.

KiCad · Python · SystemVerilog · Vivado · LTSpice

ThetaCore: RISC-V CPU Core

Project

A multicycle RISC-V R32I single-core processor with SRAM and associated assembler.

SystemVerilog · GTKWave · IcarusVerilog

ThetaCore: RISC-V CPU Core

TinyTapeout SPI/PWM Peripheral

2025

A SPI-communication PHY for control of a PWM module, synthesized with the TinyTapeout PDK.

CocoTB · Verilog · Python · GTKWave

TinyTapeout SPI/PWM Peripheral

Media Control Ground-Up Keyboard

Project

A custom Spotify control Stream Deck designed from scratch: PCB design, firmware implementation, and case modelling.

KiCad · Raspberry Pi · QMK Firmware · Fusion360

Media Control Ground-Up Keyboard

Neuromorphic Computing for Smart Cities

Paper

Matthew Chen, Iris Litiu, Christina Lu

An analysis of neuromorphic computing power efficiency and applications in IoT devices.

03Experience

Digital Systems Design Team

AlteraMay 2026 - Aug. 2026

Network on Chip IP to facillitate AXI-4 transactions with HBM controllers

Project Co-lead

UWASICJan. 2026 - Present

Design and tapeout of ASIC ray tracer

Undergraduate Research Assistant

University of WaterlooJan. 2026 - Apr. 2026

Using Xilinx FPGAs to accelerate transport-layer protocol, backpressure mechanism

Design Verification Intern

MarvellSep. 2025 - Dec. 2025

Writing UVM for functional verification of terabit/lane optical retimer

Digital Design Intern

IntelJan. 2025 - Apr. 2025

Developed 100Gbs/lane SerDes simulations on 18A

Machine Learning Research Intern

University of TorontoSummer 2023

Looked into CNN-based anomaly detection for transmission relays