2nd Order Delta-Sigma ADC
2026A continuous-time 2nd-order ΔΣ ADC, built with a 3-bit flash sampler at 10 MHz/sample and DWA element rotation, FPGA backend filtering + decimation, modelled in Python for loop stability, noise shaping, and ELD.
KiCad · Python · SystemVerilog · Vivado · LTSpice




